1. Field of Invention
The present invention relates to a switching power supply. More specifically, the present invention relates to a switching power supply with restricted switching frequency.
2. Description of Related Art
FIG. 1 illustrates a quasi-resonant fly-back converter, capable of reducing switching loss and switching noise. The converter of FIG. 1 includes an auxiliary coil LB to measure a voltage at a switch Q1, and a ZCD (zero-crossing detector) circuit to identify the instance when bias-coil voltage VB of bias coil LB crosses zero. A function of ZCD is to turn on switch Q1 at this instance, thereby reducing switching loss.
FIGS. 2A–G show voltages and currents at the indicated nodes of FIG. 1. The operation of the converter will now be described with reference to FIGS. 1 and 2.
FIG. 2F illustrates that control circuit CTL turns on switch Q1 by applying a pulse in pulse-signal V2.
FIG. 2G illustrates that the pulse in pulse-signal V2 generates a pulse in gate-source voltage VGS, a gate-source voltage of switch Q1.
FIG. 2A illustrates that a drain current ID of switch Q1 starts increasing with a gradient of about VIN/LP at the instance of the pulse. The increase of ID lasts for an on-time TON. During on-time TON the energy of a transformer T is output from its secondary coil LS, charging up a capacitor C2.
FIG. 2B illustrates a current IS of diode D2 in the secondary circuit, neglecting a forward voltage. At the end of on-time TON, current IS starts decreasing with a gradient of about −VOUT/LS until it reaches about 0V. When current IS becomes 0V, diode D2 is turned off and the secondary coil acquires a high impedance.
FIG. 2C illustrates that, as a result, the voltage at primary coil LP starts resonating. The resonance period is determined by values of inductance LP and capacitance Cr. The voltage of capacitance Cr is also the drain-source voltage VDS of switch Q1. During the resonating process voltage VDS is reduced according to the shown cosine curve.
The switching loss of a MOSFET is given as 0.5·(COSS+Cr)·VDS·VDS·f, where f is a switching frequency and COSS is a parasitic capacitance between the drain and the source of switch Q1. Accordingly, the switching loss is proportional to drain-source voltage VDS and switching frequency f.
One aspect of the converter circuit of FIG. 1 is to reduce drain-source voltage VDS, thus reducing the switching loss. This is achieved by sensing, when VDS reaches its low values about the bottom of the resonant waveform in FIG. 2C, and turning on switch Q1 at that time instance by a pulse in VGS.
FIG. 2D illustrates bias-coil voltage VB, a voltage of bias coil LB.
FIG. 2E illustrates that the instance, at which VB crosses zero, is sensed by zero-crossing detection circuit ZCD. In response, ZCD outputs a ZCD signal V1 to delay circuit DLY.
FIG. 2F illustrates that delay circuit DLY, with the help of Waveform Shaping circuit WS, generates the above-described pulse in pulse-signal V2, and outputs it to control circuit CTL after a predetermined delay time Td. In response, control circuit CTL turns on switch Q1.
The period of the converter circuit of FIG. 1 is given by T=TON+Tr+TOFF. Here, Tr is the resonant period, determined by inductance LP and capacitance Cr. The values of TON and TOFF depend on input voltage VIN and on the output load. In particular, when the output load is reduced, the period decreases, thus increasing the switching frequency. As described above, this leads to an increase of the switching loss.
Concerning related designs, U.S. Pat. No. 5,497,311 discloses a method for restricting the maximal switching frequency of quasi-resonance flyback converters by using a mono-stable multi-vibrator. This design restricts the maximum value of the switching frequency by controlling the turned-on states of switch Q1 according to the states of a mono-stable multi-vibrator. However, this design is still characterized by a high switching frequency and hence reduced efficiency.